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71M6545/71M6545H Data Sheet
Figures
Figure 1: IC Functional Block Diagram ......................................................................................................... 9
Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes) ......................................................... 12
Figure 3. AFE Block Diagram (Four CTs) ................................................................................................... 13
Figure 4: States in a Multiplexer Frame ( MUX_DIV[3:0] = 6) ..................................................................... 17
Figure 5: States in a Multiplexer Frame ( MUX_DIV[3:0] = 7) ..................................................................... 17
Figure 6: General Topology of a Chopped Amplifier .................................................................................. 20
Figure 7: CROSS Signal with CHOP_E = 00 ............................................................................................... 21
Figure 8: RTM Timing ................................................................................................................................. 26
Figure 9. Pulse Generator FIFO Timing ...................................................................................................... 28
Figure 10: Samples from Multiplexer Cycle (Frame) .................................................................................. 29
Figure 11: Accumulation Interval ................................................................................................................ 29
Figure 12: Interrupt Structure ...................................................................................................................... 45
Figure 13: Automatic Temperature Compensation ..................................................................................... 52
Figure 14: Connecting an External Load to DIO Pins ................................................................................. 57
Figure 15: 3-wire Interface. Write Command, HiZ=0. ................................................................................ 59
Figure 16: 3-wire Interface. Write Command, HiZ=1 ................................................................................. 59
Figure 17: 3-wire Interface. Read Command. ............................................................................................ 59
Figure 18: 3-Wire Interface. Write Command when CNT=0 ...................................................................... 59
Figure 19: 3-wire Interface. Write Command when HiZ=1 and WFR=1. ................................................... 59
Figure 20: SPI Slave Port - Typical Multi-Byte Read and Write operations ................................................ 61
Figure 21: Voltage, Current, Momentary and Accumulated Energy ........................................................... 66
Figure 22: Data Flow ................................................................................................................................... 69
Figure 23: Resistive Voltage Divider (Voltage Sensing) ............................................................................. 71
Figure 24. CT with Single-Ended Input Connection (Current Sensing) ...................................................... 71
Figure 25: CT with Differential Input Connection (Current Sensing) .......................................................... 71
Figure 26: Differential Resistive Shunt Connections (Current Sensing) ..................................................... 71
Figure 27: System Using Three-Remotes and One-Local (Neutral) Sensor .............................................. 72
Figure 28. System Using Current Transformers ......................................................................................... 73
Figure 29: I 2 C EEPROM Connection .......................................................................................................... 79
Figure 30: Connections for the UART ......................................................................................................... 79
Figure 31: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) ........ 80
Figure 32: External Components for the Emulator Interface ...................................................................... 80
Figure 33. Trim Fuse Bit Mapping ............................................................................................................... 98
Figure 34: CE Data Flow: Multiplexer and ADC........................................................................................ 111
Figure 35: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase ......................... 111
Figure 36: CE Data Flow: Squaring and Summation Stages .................................................................... 112
Figure 37: 64-pin LQFP Package Outline ................................................................................................. 125
Figure 38: Pinout for the LQFP-64 Package ............................................................................................. 126
Figure 39: I/O Equivalent Circuits ............................................................................................................. 130
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